Dictionary¶
Stack Jugglers¶
Single-Jugglers¶
nip ( x1 x2 -- x2 )
drop ( x -- )
rot ( x1 x2 x3 -- x2 x3 x1 )
-rot ( x1 x2 x3 -- x3 x1 x2 )
swap ( x1 x2 -- x2 x1 )
tuck ( x1 x2 -- x2 x1 x2 )
over ( x1 x2 -- x1 x2 x1 )
?dup ( x -- 0 | x x )
dup ( x -- x x )
>r ( x -- ) (R: -- x )
r> ( -- x ) (R: x -- )
r@ ( -- x ) (R: x -- x )
rdrop ( -- ) (R: x -- )
Double-Jugglers¶
They perform the same for double numbers.
2drop ( x1 x2 -- )
2dup ( x1 x2 -- x1 x2 x1 x2 )
2swap ( x1 x2 x3 x4 -- x3 x4 x1 x2 )
Logic¶
arshift ( x1 u -- x2 ) Arithmetric right-shift of u bit-places
rshift ( x1 u -- x2 ) Logical right-shift of u bit-places
lshift ( x1 u -- x2 ) Logical left-shift of u bit-places
shr ( x1 -- x2 ) Logical right-shift of one bit-place
shl ( x1 -- x2 ) Logical left-shift of one bit-place
ror ( x1 -- x2 ) Logical right-rotation of one bit-place
rol ( x1 -- x2 ) Logical left-rotation of one bit-place
bic ( x1 x2 -- x3 ) Bit clear, identical to "not and"
not ( x1 -- x2 ) Invert all bits
xor ( x1 x2 -- x3 ) Bitwise Exclusive-OR
or ( x1 x2 -- x3 ) Bitwise OR
and ( x1 x2 -- x3 ) Bitwise AND
false ( -- 0 ) False-Flag
true ( -- -1 ) True-Flag
>< ( xy -- yx ) Swap bytes
Arithmetic for single numbers¶
\* ( u1|n1 u2|n2 -- u3|n3 ) 16*16 = 16 Multiplication
2* ( n1 -- n2 ) Arithmetric left-shift
2/ ( n1 -- n2 ) Arithmetric right-shift
negate ( n1 -- n2 ) Negate
- ( u1|n1 u2|n2 -- u3|n3 ) Subtraction
+ ( u1|n1 u2|n2 -- u3|n3 ) Addition
Arithmetic involving double numbers¶
d2* ( d1 -- d2 ) Arithmetric left-shift
d2/ ( d1 -- d2 ) Arithmetric right-shift
dshl ( ud1 -- ud2 ) Logical left-shift, same as d2*
dshr ( ud1 -- ud2 ) Logical right-shift
d- ( ud1|d1 ud2|d2 -- ud3|d3 ) Subtraction
d+ ( ud1|d1 ud2|d2 -- ud3|d3 ) Addition
Arithmetic without special optimisations¶
abs ( n -- u ) Absolute value
dabs ( d -- ud ) Absolute value
dnegate ( d1 -- d2 ) Negate
s>d ( n -- d ) Makes a signed single number double length
um* ( u1 u2 -- ud ) 16*16 = 32 Multiplication
um/mod ( ud u1 -- u2 u3 ) ud / u1 = u3 remainder u2
m* ( n1 n2 -- d ) n1 * n2 = d
fm/mod ( d n1 -- n2 n3 ) d / n1 = n3 remainder r2 floored
sm/rem ( d n1 -- n2 n3 ) d / n1 = n3 remainder r2 symmetric
/mod ( n1 n2 -- n3 n4 ) n1 / n2 = n4 rem n3
mod ( n1 n2 -- n3 ) n1 / n2 = remainder n3
/ ( n1 n2 -- n3 ) n1 / n2 = n3
*/ ( n1 n2 n3 -- n4 ) n1 * n2 / n3 = n4
*/mod ( n1 n2 n3 -- n4 n5 ) n1 * n2 / n3 = n5 remainder n4
Comparisions¶
u<= ( u1 u2 -- flag ) Unsigned comparisions
u>= ( u1 u2 -- flag )
u> ( u1 u2 -- flag )
u< ( u1 u2 -- flag )
<= ( n1 n2 -- flag ) Signed comparisions
>= ( n1 n2 -- flag )
> ( n1 n2 -- flag )
< ( n1 n2 -- flag )
0< ( n - flag ) Negative ?
0<> ( x -- flag )
0= ( x -- flag )
<> ( x1 x2 -- flag )
= ( x1 x2 -- flag )
Memory access¶
cbit@ ( mask c-addr -- flag ) Test BIts in byte-location
bit@ ( mask a-addr -- flag ) Test BIts in word-location
cxor! ( mask c-addr -- ) Toggle bits in byte-location
xor! ( mask a-addr -- ) Toggle bits in word-location
cbic! ( mask c-addr -- ) Clear BIts in byte-location
bic! ( mask a-addr -- ) Clear BIts in word-location
cbis! ( mask c-addr -- ) Set BIts in byte-location
bis! ( mask a-addr -- ) Set BIts in word-location
constant name ( u|n -- ) Makes a single constant.
variable name ( n|n -- ) Makes an initialized single variable
buffer: name ( u -- ) Creates a buffer in RAM with u bytes length
@ ( a-addr -- u|n ) Fetches single number from memory
! ( u|n a-addr -- ) Stores single number in memory
+! ( u|n a-addr -- ) Add to memory location
c@ ( c-addr -- char ) Fetches byte from memory
c! ( char c-addr ) Stores byte in memory
c+! ( u|n a-addr -- ) Add to byte memory location
Flags and inventory¶
inline ( -- ) Makes current definition always inlineable.
immediate ( -- ) Makes current definition immediate.
0-foldable ( -- ) Current word becomes foldable with zero constants
1-foldable ( -- ) Current word becomes foldable with one constants
2-foldable ( -- ) Current word becomes foldable with two constants
3-foldable ( -- ) Current word becomes foldable with three constants
...
7-foldable ( -- ) Current word becomes foldable with seven constants
Compiler essentials¶
postpone name ( -- ) Helps compiling immediate words.
does> ( -- ) executes: ( -- a-addr ) Gives address to where you have stored data.
<builds ( -- ) Makes Dictionary header and reserves space for special call.
create name ( -- ) Create a constant table.
endcreate ( -- ) Finish a constant table
] ( -- ) Switch to compile state
[ ( -- ) Switch to execute state
; ( -- ) Finishes new definition
: name ( -- ) Opens new definition
, ( u|n -- ) Appends a single number to dictionary
[char] * ( -- char) Compiles code of following char when executed
char * ( -- char ) gives code of following char
Control structures¶
Decisions:
flag if ... then
flag if ... else ... then
then ( -- ) This is the common
else ( -- ) flag if ... [else ...] then
if ( flag -- ) structure.
ahead ( -- )
Case:
n case
m1 of ... endof
m2 .. ... .....
all others
endcase
case ( n -- n ) Begins case structure
of ( m -- ) Compares m with n, choose this if n=m
endof ( -- ) End of one possibility
endcase ( n -- ) Ends case structure, discards n
Indefinite Loops:
begin ... again
begin ... flag until
begin ... flag while ... repeat
repeat ( -- ) Finish of a middle-flag-checking loop.
while ( flag -- ) Check a flag in the middle of a loop
until ( flag -- ) begin ... flag until loops until flag is true
again ( -- ) begin ... again is an endless loop
begin ( -- ) is an endless loop
Definite Loops:
limit index do ... [one or more leave(s)] ... loop
?do ... [one or more leave(s)] ... loop
j ( -- u|n ) Gives second loop index
i ( -- u|n ) Gives innermost loop index
unloop (R: old-limit old-index -- )
Drops innermost loop structure,
pops back old loop structures to loop registers
exit ( -- ) Returns from current definition.
Compiles a ret opcode.
leave ( -- ) (R: old-limit old-index -- )
Leaves current innermost loop promptly
loop ( -- )
(R: unchanged | old-limit old-index -- )
Increments current loop index register by one
and checks whether to continue or not.
?do ( Limit Index -- )
(R: unchanged | -- old-limit old-index )
Begins a loop if limit and index are not equal
do ( Limit Index -- )
(R: -- old-limit old-index )
Begins a loop
Reset, Interrupts and Low Power Modes¶
Including five low power modes.
reset ( -- ) Reset on hardware level by triggering Watchdog
dint ( -- ) Disables Interrupts
eint ( -- ) Enables Interrupts
ie1 ?
ie2 ?
lpm0 ( -- ) Enter LPM0 and enable IRQs:
CPU, MCLK are disabled.
SMCLK, ACLK are active
lpm1 ( -- ) Enter LPM1 and enable IRQs:
CPU, MCLK are disabled.
DCO and DC generator are disabled if
the DCO is not used for SMCLK.
ACLK is active.
lpm2 ( -- ) Enter LPM2 and enable IRQs:
CPU, MCLK, SMCLK, DCO are disabled.
DC generator remains enabled.
ACLK is active.
lpm3 ( -- ) Enter LPM3 and enable IRQs:
CPU, MCLK, SMCLK, DCO are disabled.
DC generator disabled.
ACLK is active.
lpm4 ( -- ) Enter LPM4 and enable IRQs:
CPU and all clocks disabled.
wakeup ( -- ) Gives the current vector the ability to wake
from sleep modes upon return.
This is a flag and cannot be used conditionally
Clock setup¶
1MHz ( -- ) Load DCO calibration values
8MHz ( -- )
12MHz ( -- )
16MHz ( -- )
Terminal-IO¶
Included for MSP430G2553 and emulation
uart-init ( -- ) Prepare UART for 9600 Baud @ 8 MHz
emit? ( -- Flag ) Ready to send a character ?
key? ( -- Flag ) Checks if a key is waiting
key ( -- Char ) Waits for and fetches the pressed key
emit ( Char -- ) Emits a character.
cr ( -- ) Emits line feed
space ( -- ) Emits space
hex. ( u -- ) Prints 16 bit unsigned in hex base.
Pictured Numerical Output¶
Note
Large due to a lot of dependencies !
output-base ( -- a-addr ) Number base variable for pictured output
hold ( char -- ) Adds character to pictured number output buffer from the front.
sign ( n -- ) Add a minus sign to pictured number output buffer, if n is negative
#S ( ud1|d1 -- 0 0 ) Add all remaining digits from the double length number to output buffer
# ( ud1|d1 -- ud2|d2 ) Add one digit from the double length number to output buffer
#> ( ud|d -- c-addr len ) Drops double-length number and finishes pictured numeric output ready for type
<# ( -- ) Prepare pictured number output buffer
u. ( u -- ) Print unsigned single number
. ( n -- ) Print single number
ud. ( ud -- ) Print unsigned double number
d. ( d -- ) Print double number
rtype ( addr len n -- ) Display string in field n characters wide
u.r ( u n -- ) Print unsigned single number in field n characters wide
.r ( n n -- ) Print single number in field n characters wide
ud.r ( ud n -- ) Print unsigned double number in field n characters wide
d.r ( d n -- ) Print double number in field n characters wide
Target only tools available during development¶
words ( -- ) Prints list of defined words.
list ( -- ) Prints a short overview of defined words.
.s ( many -- many ) Prints stack contents, hexadecimal
see name ( -- ) Insight into definitions
binary ( -- ) Sets base to 2
decimal ( -- ) Sets base to 10
hex ( -- ) Sets base to 16
u. ( u -- ) Print unsigned single number
. ( n -- ) Print single number
bin. ( n -- binary print ) print any number as a 16 bit binary (no bit position legend)
Predefined Port Constants¶
These are simply memory mapped Words, created by svd2forth-msp430
\ Memory Map file for MSP430G2553
\ created by svdcutter for Mecrisp Forth by Matthias Koch
\ sdvcutter takes a MSP430xx SVD file created by https://github.com/pftbest/msp430_svd and creates a memmap, register and config.xml file.
\ The config.xml file may be edited to control the size of the memmap file
\ By Terry Porter copyright 2020 released under the MIT Licence.
\ ***** Flash ***** \
$128 constant FCTL1 \ FLASH Control 1
$12A constant FCTL2 \ FLASH Control 2
$12C constant FCTL3 \ FLASH Control 3
\ ***** USCI_A0_UART_Mode ***** \
$5D constant UCA0ABCTL \ USCI A0 LIN Control
$5E constant UCA0IRTCTL \ USCI A0 IrDA Transmit Control
$5F constant UCA0IRRCTL \ USCI A0 IrDA Receive Control
$60 constant UCA0CTL0 \ USCI A0 Control Register 0
$61 constant UCA0CTL1 \ USCI A0 Control Register 1
$62 constant UCA0BR0 \ USCI A0 Baud Rate 0
$63 constant UCA0BR1 \ USCI A0 Baud Rate 1
$64 constant UCA0MCTL \ USCI A0 Modulation Control
$65 constant UCA0STAT \ USCI A0 Status Register
$66 constant UCA0RXBUF \ USCI A0 Receive Buffer
$67 constant UCA0TXBUF \ USCI A0 Transmit Buffer
\ ***** Watchdog_Timer ***** \
$120 constant WDTCTL \ Watchdog Timer Control
\ ***** Comparator_A ***** \
$59 constant CACTL1 \ Comparator A Control 1
$5A constant CACTL2 \ Comparator A Control 2
$5B constant CAPD \ Comparator A Port Disable
\ ***** Timer1_A3 ***** \
$11E constant TA1IV \ Timer1_A3 Interrupt Vector Word
$180 constant TA1CTL \ Timer1_A3 Control
$182 constant TA1CCTL0 \ Timer1_A3 Capture/Compare Control 0
$184 constant TA1CCTL1 \ Timer1_A3 Capture/Compare Control 1
$186 constant TA1CCTL2 \ Timer1_A3 Capture/Compare Control 2
$190 constant TA1R \ Timer1_A3 Counter Register
$192 constant TA1CCR0 \ Timer1_A3 Capture/Compare 0
$194 constant TA1CCR1 \ Timer1_A3 Capture/Compare 1
$196 constant TA1CCR2 \ Timer1_A3 Capture/Compare 2
\ ***** Timer0_A3 ***** \
$12E constant TA0IV \ Timer0_A3 Interrupt Vector Word
$160 constant TA0CTL \ Timer0_A3 Control
$162 constant TA0CCTL0 \ Timer0_A3 Capture/Compare Control 0
$164 constant TA0CCTL1 \ Timer0_A3 Capture/Compare Control 1
$166 constant TA0CCTL2 \ Timer0_A3 Capture/Compare Control 2
$170 constant TA0R \ Timer0_A3 Counter Register
$172 constant TA0CCR0 \ Timer0_A3 Capture/Compare 0
$174 constant TA0CCR1 \ Timer0_A3 Capture/Compare 1
$176 constant TA0CCR2 \ Timer0_A3 Capture/Compare 2
\ ***** USCI_B0_I2C_Mode ***** \
$68 constant UCB0CTL0 \ USCI B0 Control Register 0
$69 constant UCB0CTL1 \ USCI B0 Control Register 1
$6A constant UCB0BR0 \ USCI B0 Baud Rate 0
$6B constant UCB0BR1 \ USCI B0 Baud Rate 1
$6C constant UCB0I2CIE \ USCI B0 I2C Interrupt Enable Register
$6D constant UCB0STAT \ USCI B0 Status Register
$6E constant UCB0RXBUF \ USCI B0 Receive Buffer
$6F constant UCB0TXBUF \ USCI B0 Transmit Buffer
$118 constant UCB0I2COA \ USCI B0 I2C Own Address
$11A constant UCB0I2CSA \ USCI B0 I2C Slave Address
\ ***** TLV_Calibration_Data ***** \
$10DA constant TLV_ADC10_1_TAG \ TLV ADC10_1 TAG
$10DB constant TLV_ADC10_1_LEN \ TLV ADC10_1 LEN
$10F6 constant TLV_DCO_30_TAG \ TLV TAG_DCO30 TAG
$10F7 constant TLV_DCO_30_LEN \ TLV TAG_DCO30 LEN
$10C0 constant TLV_CHECKSUM \ TLV CHECK SUM
\ ***** ADC10 ***** \
$48 constant ADC10DTC0 \ ADC10 Data Transfer Control 0
$49 constant ADC10DTC1 \ ADC10 Data Transfer Control 1
$4A constant ADC10AE0 \ ADC10 Analog Enable 0
$1B0 constant ADC10CTL0 \ ADC10 Control 0
$1B2 constant ADC10CTL1 \ ADC10 Control 1
$1B4 constant ADC10MEM \ ADC10 Memory
$1BC constant ADC10SA \ ADC10 Data Transfer Start Address
\ ***** USCI_B0_SPI_Mode ***** \
$68 constant UCB0CTL0 \ USCI B0 Control Register 0
$69 constant UCB0CTL1 \ USCI B0 Control Register 1
$6A constant UCB0BR0 \ USCI B0 Baud Rate 0
$6B constant UCB0BR1 \ USCI B0 Baud Rate 1
$6D constant UCB0STAT \ USCI B0 Status Register
$6E constant UCB0RXBUF \ USCI B0 Receive Buffer
$6F constant UCB0TXBUF \ USCI B0 Transmit Buffer
\ ***** USCI_A0_SPI_Mode ***** \
$60 constant UCA0CTL0 \ USCI A0 Control Register 0
$61 constant UCA0CTL1 \ USCI A0 Control Register 1
$62 constant UCA0BR0 \ USCI A0 Baud Rate 0
$63 constant UCA0BR1 \ USCI A0 Baud Rate 1
$64 constant UCA0MCTL \ USCI A0 Modulation Control
$65 constant UCA0STAT \ USCI A0 Status Register
$66 constant UCA0RXBUF \ USCI A0 Receive Buffer
$67 constant UCA0TXBUF \ USCI A0 Transmit Buffer
\ ***** Special_Function ***** \
$ constant IE1 \ Interrupt Enable 1
$1 constant IE2 \ Interrupt Enable 2
$2 constant IFG1 \ Interrupt Flag 1
$3 constant IFG2 \ Interrupt Flag 2
\ ***** Port_3_4 ***** \
$10 constant P3REN \ Port 3 Resistor Enable
$18 constant P3IN \ Port 3 Input
$19 constant P3OUT \ Port 3 Output
$1A constant P3DIR \ Port 3 Direction
$1B constant P3SEL \ Port 3 Selection
$43 constant P3SEL2 \ Port 3 Selection 2
\ ***** Calibration_Data ***** \
$10F8 constant CALDCO_16MHZ \ DCOCTL Calibration Data for 16MHz
$10F9 constant CALBC1_16MHZ \ BCSCTL1 Calibration Data for 16MHz
$10FA constant CALDCO_12MHZ \ DCOCTL Calibration Data for 12MHz
$10FB constant CALBC1_12MHZ \ BCSCTL1 Calibration Data for 12MHz
$10FC constant CALDCO_8MHZ \ DCOCTL Calibration Data for 8MHz
$10FD constant CALBC1_8MHZ \ BCSCTL1 Calibration Data for 8MHz
$10FE constant CALDCO_1MHZ \ DCOCTL Calibration Data for 1MHz
$10FF constant CALBC1_1MHZ \ BCSCTL1 Calibration Data for 1MHz
\ ***** Port_1_2 ***** \
$20 constant P1IN \ Port 1 Input
$21 constant P1OUT \ Port 1 Output
$22 constant P1DIR \ Port 1 Direction
$23 constant P1IFG \ Port 1 Interrupt Flag
$24 constant P1IES \ Port 1 Interrupt Edge Select
$25 constant P1IE \ Port 1 Interrupt Enable
$26 constant P1SEL \ Port 1 Selection
$27 constant P1REN \ Port 1 Resistor Enable
$28 constant P2IN \ Port 2 Input
$29 constant P2OUT \ Port 2 Output
$2A constant P2DIR \ Port 2 Direction
$2B constant P2IFG \ Port 2 Interrupt Flag
$2C constant P2IES \ Port 2 Interrupt Edge Select
$2D constant P2IE \ Port 2 Interrupt Enable
$2E constant P2SEL \ Port 2 Selection
$2F constant P2REN \ Port 2 Resistor Enable
$41 constant P1SEL2 \ Port 1 Selection 2
$42 constant P2SEL2 \ Port 2 Selection 2
\ ***** System_Clock ***** \
$53 constant BCSCTL3 \ Basic Clock System Control 3
$56 constant DCOCTL \ DCO Clock Frequency Control
$57 constant BCSCTL1 \ Basic Clock System Control 1
$58 constant BCSCTL2 \ Basic Clock System Control 2
\ ***** _INTERRUPTS ***** \
