MSP430G2553 register Word generation reference file for Mecrisp-Stellaris Forth by Matthias Koch. Uses registers.xsl and your config.xml file. Do not load this file, just copy and paste what you need into your source file. Written by Terry Porter 2022. Released under the MIT Licence =================================== Flash =================================== \ FCTL1 : FLASH Control 1 : FCTL1_ERASE ( -- x ) %1 1 lshift ; \ Enable bit for Flash segment erase : FCTL1_MERAS ( -- x ) %1 2 lshift ; \ Enable bit for Flash mass erase : FCTL1_WRT ( -- x ) %1 6 lshift ; \ Enable bit for Flash write : FCTL1_BLKWRT ( -- x ) %1 7 lshift ; \ Enable bit for Flash segment write \ FCTL2 : FLASH Control 2 : FCTL2_FN0 ( -- x ) %1 0 lshift ; \ Divide Flash clock by 1 to 64 using FN0 to FN5 according to: : FCTL2_FN1 ( -- x ) %1 1 lshift ; \ 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 : FCTL2_FN2 ( -- x ) %1 2 lshift ; \ FN2 : FCTL2_FN3 ( -- x ) %1 3 lshift ; \ FN3 : FCTL2_FN4 ( -- x ) %1 4 lshift ; \ FN4 : FCTL2_FN5 ( -- x ) %1 5 lshift ; \ FN5 : FCTL2_FSSEL<< ( x -- ) 6 lshift ; \ Flash clock select 0 */ /* to distinguish from USART SSELx 0 constant FSSEL_0 \ Flash clock select: 0 - ACLK 1 constant FSSEL_1 \ Flash clock select: 1 - MCLK 2 constant FSSEL_2 \ Flash clock select: 2 - SMCLK 3 constant FSSEL_3 \ Flash clock select: 3 - SMCLK \ FCTL3 : FLASH Control 3 : FCTL3_BUSY ( -- x ) %1 0 lshift ; \ Flash busy: 1 : FCTL3_KEYV ( -- x ) %1 1 lshift ; \ Flash Key violation flag : FCTL3_ACCVIFG ( -- x ) %1 2 lshift ; \ Flash Access violation flag : FCTL3_WAIT ( -- x ) %1 3 lshift ; \ Wait flag for segment write : FCTL3_LOCK ( -- x ) %1 4 lshift ; \ Lock bit: 1 - Flash is locked (read only) : FCTL3_EMEX ( -- x ) %1 5 lshift ; \ Flash Emergency Exit : FCTL3_LOCKA ( -- x ) %1 6 lshift ; \ Segment A Lock bit: read = 1 - Segment is locked (read only) : FCTL3_FAIL ( -- x ) %1 7 lshift ; \ Last Program or Erase failed =================================== USCI_A0_UART_Mode =================================== \ UCA0ABCTL : USCI A0 LIN Control : UCA0ABCTL_UCABDEN ( -- x ) %1 0 lshift ; \ Auto Baud Rate detect enable : UCA0ABCTL_UCBTOE ( -- x ) %1 2 lshift ; \ Break Timeout error : UCA0ABCTL_UCSTOE ( -- x ) %1 3 lshift ; \ Sync-Field Timeout error : UCA0ABCTL_UCDELIM0 ( -- x ) %1 4 lshift ; \ Break Sync Delimiter 0 : UCA0ABCTL_UCDELIM1 ( -- x ) %1 5 lshift ; \ Break Sync Delimiter 1 \ UCA0IRTCTL : USCI A0 IrDA Transmit Control : UCA0IRTCTL_UCIREN ( -- x ) %1 0 lshift ; \ IRDA Encoder/Decoder enable : UCA0IRTCTL_UCIRTXCLK ( -- x ) %1 1 lshift ; \ IRDA Transmit Pulse Clock Select : UCA0IRTCTL_UCIRTXPL0 ( -- x ) %1 2 lshift ; \ IRDA Transmit Pulse Length 0 : UCA0IRTCTL_UCIRTXPL1 ( -- x ) %1 3 lshift ; \ IRDA Transmit Pulse Length 1 : UCA0IRTCTL_UCIRTXPL2 ( -- x ) %1 4 lshift ; \ IRDA Transmit Pulse Length 2 : UCA0IRTCTL_UCIRTXPL3 ( -- x ) %1 5 lshift ; \ IRDA Transmit Pulse Length 3 : UCA0IRTCTL_UCIRTXPL4 ( -- x ) %1 6 lshift ; \ IRDA Transmit Pulse Length 4 : UCA0IRTCTL_UCIRTXPL5 ( -- x ) %1 7 lshift ; \ IRDA Transmit Pulse Length 5 \ UCA0IRRCTL : USCI A0 IrDA Receive Control : UCA0IRRCTL_UCIRRXFE ( -- x ) %1 0 lshift ; \ IRDA Receive Filter enable : UCA0IRRCTL_UCIRRXPL ( -- x ) %1 1 lshift ; \ IRDA Receive Input Polarity : UCA0IRRCTL_UCIRRXFL0 ( -- x ) %1 2 lshift ; \ IRDA Receive Filter Length 0 : UCA0IRRCTL_UCIRRXFL1 ( -- x ) %1 3 lshift ; \ IRDA Receive Filter Length 1 : UCA0IRRCTL_UCIRRXFL2 ( -- x ) %1 4 lshift ; \ IRDA Receive Filter Length 2 : UCA0IRRCTL_UCIRRXFL3 ( -- x ) %1 5 lshift ; \ IRDA Receive Filter Length 3 : UCA0IRRCTL_UCIRRXFL4 ( -- x ) %1 6 lshift ; \ IRDA Receive Filter Length 4 : UCA0IRRCTL_UCIRRXFL5 ( -- x ) %1 7 lshift ; \ IRDA Receive Filter Length 5 \ UCA0CTL0 : USCI A0 Control Register 0 : UCA0CTL0_UCSYNC ( -- x ) %1 0 lshift ; \ Sync-Mode 0:UART-Mode / 1:SPI-Mode : UCA0CTL0_UCMODE<< ( x -- ) 1 lshift ; \ Async. Mode: USCI Mode 1 0 constant UCMODE_0 \ Sync. Mode: USCI Mode: 0 1 constant UCMODE_1 \ Sync. Mode: USCI Mode: 1 2 constant UCMODE_2 \ Sync. Mode: USCI Mode: 2 3 constant UCMODE_3 \ Sync. Mode: USCI Mode: 3 : UCA0CTL0_UCSPB ( -- x ) %1 3 lshift ; \ Async. Mode: Stop Bits 0:one / 1: two : UCA0CTL0_UC7BIT ( -- x ) %1 4 lshift ; \ Async. Mode: Data Bits 0:8-bits / 1:7-bits : UCA0CTL0_UCMSB ( -- x ) %1 5 lshift ; \ Async. Mode: MSB first 0:LSB / 1:MSB : UCA0CTL0_UCPAR ( -- x ) %1 6 lshift ; \ Async. Mode: Parity 0:odd / 1:even : UCA0CTL0_UCPEN ( -- x ) %1 7 lshift ; \ Async. Mode: Parity enable \ UCA0CTL1 : USCI A0 Control Register 1 : UCA0CTL1_UCSWRST ( -- x ) %1 0 lshift ; \ USCI Software Reset : UCA0CTL1_UCTXBRK ( -- x ) %1 1 lshift ; \ Send next Data as Break : UCA0CTL1_UCTXADDR ( -- x ) %1 2 lshift ; \ Send next Data as Address : UCA0CTL1_UCDORM ( -- x ) %1 3 lshift ; \ Dormant (Sleep) Mode : UCA0CTL1_UCBRKIE ( -- x ) %1 4 lshift ; \ Break interrupt enable : UCA0CTL1_UCRXEIE ( -- x ) %1 5 lshift ; \ RX Error interrupt enable : UCA0CTL1_UCSSEL<< ( x -- ) 6 lshift ; \ USCI 0 Clock Source Select 1 0 constant UCSSEL_0 \ USCI 0 Clock Source: 0 1 constant UCSSEL_1 \ USCI 0 Clock Source: 1 2 constant UCSSEL_2 \ USCI 0 Clock Source: 2 3 constant UCSSEL_3 \ USCI 0 Clock Source: 3 \ UCA0BR0 : USCI A0 Baud Rate 0 \ UCA0BR1 : USCI A0 Baud Rate 1 \ UCA0MCTL : USCI A0 Modulation Control : UCA0MCTL_UCOS16 ( -- x ) %1 0 lshift ; \ USCI 16-times Oversampling enable : UCA0MCTL_UCBRS<< ( x -- ) 1 lshift ; \ USCI Second Stage Modulation Select 2 0 constant UCBRS_0 \ USCI Second Stage Modulation: 0 1 constant UCBRS_1 \ USCI Second Stage Modulation: 1 2 constant UCBRS_2 \ USCI Second Stage Modulation: 2 3 constant UCBRS_3 \ USCI Second Stage Modulation: 3 4 constant UCBRS_4 \ USCI Second Stage Modulation: 4 5 constant UCBRS_5 \ USCI Second Stage Modulation: 5 6 constant UCBRS_6 \ USCI Second Stage Modulation: 6 7 constant UCBRS_7 \ USCI Second Stage Modulation: 7 : UCA0MCTL_UCBRF<< ( x -- ) 4 lshift ; \ USCI First Stage Modulation Select 3 0 constant UCBRF_0 \ USCI First Stage Modulation: 0 1 constant UCBRF_1 \ USCI First Stage Modulation: 1 2 constant UCBRF_2 \ USCI First Stage Modulation: 2 3 constant UCBRF_3 \ USCI First Stage Modulation: 3 4 constant UCBRF_4 \ USCI First Stage Modulation: 4 5 constant UCBRF_5 \ USCI First Stage Modulation: 5 6 constant UCBRF_6 \ USCI First Stage Modulation: 6 7 constant UCBRF_7 \ USCI First Stage Modulation: 7 8 constant UCBRF_8 \ USCI First Stage Modulation: 8 9 constant UCBRF_9 \ USCI First Stage Modulation: 9 10 constant UCBRF_10 \ USCI First Stage Modulation: A 11 constant UCBRF_11 \ USCI First Stage Modulation: B 12 constant UCBRF_12 \ USCI First Stage Modulation: C 13 constant UCBRF_13 \ USCI First Stage Modulation: D 14 constant UCBRF_14 \ USCI First Stage Modulation: E 15 constant UCBRF_15 \ USCI First Stage Modulation: F \ UCA0STAT : USCI A0 Status Register : UCA0STAT_UCBUSY ( -- x ) %1 0 lshift ; \ USCI Busy Flag : UCA0STAT_UCADDR ( -- x ) %1 1 lshift ; \ USCI Address received Flag : UCA0STAT_UCRXERR ( -- x ) %1 2 lshift ; \ USCI RX Error Flag : UCA0STAT_UCBRK ( -- x ) %1 3 lshift ; \ USCI Break received : UCA0STAT_UCPE ( -- x ) %1 4 lshift ; \ USCI Parity Error Flag : UCA0STAT_UCOE ( -- x ) %1 5 lshift ; \ USCI Overrun Error Flag : UCA0STAT_UCFE ( -- x ) %1 6 lshift ; \ USCI Frame Error Flag : UCA0STAT_UCLISTEN ( -- x ) %1 7 lshift ; \ USCI Listen mode \ UCA0RXBUF : USCI A0 Receive Buffer \ UCA0TXBUF : USCI A0 Transmit Buffer =================================== Watchdog_Timer =================================== \ WDTCTL : Watchdog Timer Control : WDTCTL_WDTIS0 ( -- x ) %1 0 lshift ; \ WDTIS0 : WDTCTL_WDTIS1 ( -- x ) %1 1 lshift ; \ WDTIS1 : WDTCTL_WDTSSEL ( -- x ) %1 2 lshift ; \ WDTSSEL : WDTCTL_WDTCNTCL ( -- x ) %1 3 lshift ; \ WDTCNTCL : WDTCTL_WDTTMSEL ( -- x ) %1 4 lshift ; \ WDTTMSEL : WDTCTL_WDTNMI ( -- x ) %1 5 lshift ; \ WDTNMI : WDTCTL_WDTNMIES ( -- x ) %1 6 lshift ; \ WDTNMIES : WDTCTL_WDTHOLD ( -- x ) %1 7 lshift ; \ WDTHOLD =================================== Comparator_A =================================== \ CACTL1 : Comparator A Control 1 : CACTL1_CAIFG ( -- x ) %1 0 lshift ; \ Comp. A Interrupt Flag : CACTL1_CAIE ( -- x ) %1 1 lshift ; \ Comp. A Interrupt Enable : CACTL1_CAIES ( -- x ) %1 2 lshift ; \ Comp. A Int. Edge Select: 0:rising / 1:falling : CACTL1_CAON ( -- x ) %1 3 lshift ; \ Comp. A enable : CACTL1_CAREF<< ( x -- ) 4 lshift ; \ Comp. A Internal Reference Select 0 0 constant CAREF_0 \ Comp. A Int. Ref. Select 0 : Off 1 constant CAREF_1 \ Comp. A Int. Ref. Select 1 : 0.25*Vcc 2 constant CAREF_2 \ Comp. A Int. Ref. Select 2 : 0.5*Vcc 3 constant CAREF_3 \ Comp. A Int. Ref. Select 3 : Vt : CACTL1_CARSEL ( -- x ) %1 6 lshift ; \ Comp. A Internal Reference Enable : CACTL1_CAEX ( -- x ) %1 7 lshift ; \ Comp. A Exchange Inputs \ CACTL2 : Comparator A Control 2 : CACTL2_CAOUT ( -- x ) %1 0 lshift ; \ Comp. A Output : CACTL2_CAF ( -- x ) %1 1 lshift ; \ Comp. A Enable Output Filter : CACTL2_P2CA0 ( -- x ) %1 2 lshift ; \ Comp. A +Terminal Multiplexer : CACTL2_P2CA1 ( -- x ) %1 3 lshift ; \ Comp. A -Terminal Multiplexer : CACTL2_P2CA2 ( -- x ) %1 4 lshift ; \ Comp. A -Terminal Multiplexer : CACTL2_P2CA3 ( -- x ) %1 5 lshift ; \ Comp. A -Terminal Multiplexer : CACTL2_P2CA4 ( -- x ) %1 6 lshift ; \ Comp. A +Terminal Multiplexer : CACTL2_CASHORT ( -- x ) %1 7 lshift ; \ Comp. A Short + and - Terminals \ CAPD : Comparator A Port Disable : CAPD_CAPD0 ( -- x ) %1 0 lshift ; \ Comp. A Disable Input Buffer of Port Register .0 : CAPD_CAPD1 ( -- x ) %1 1 lshift ; \ Comp. A Disable Input Buffer of Port Register .1 : CAPD_CAPD2 ( -- x ) %1 2 lshift ; \ Comp. A Disable Input Buffer of Port Register .2 : CAPD_CAPD3 ( -- x ) %1 3 lshift ; \ Comp. A Disable Input Buffer of Port Register .3 : CAPD_CAPD4 ( -- x ) %1 4 lshift ; \ Comp. A Disable Input Buffer of Port Register .4 : CAPD_CAPD5 ( -- x ) %1 5 lshift ; \ Comp. A Disable Input Buffer of Port Register .5 : CAPD_CAPD6 ( -- x ) %1 6 lshift ; \ Comp. A Disable Input Buffer of Port Register .6 : CAPD_CAPD7 ( -- x ) %1 7 lshift ; \ Comp. A Disable Input Buffer of Port Register .7 =================================== Timer1_A3 =================================== \ TA1IV : Timer1_A3 Interrupt Vector Word \ TA1CTL : Timer1_A3 Control : TA1CTL_TAIFG ( -- x ) %1 0 lshift ; \ Timer A counter interrupt flag : TA1CTL_TAIE ( -- x ) %1 1 lshift ; \ Timer A counter interrupt enable : TA1CTL_TACLR ( -- x ) %1 2 lshift ; \ Timer A counter clear : TA1CTL_MC<< ( x -- ) 4 lshift ; \ Timer A mode control 1 0 constant MC_0 \ Timer A mode control: 0 - Stop 1 constant MC_1 \ Timer A mode control: 1 - Up to CCR0 2 constant MC_2 \ Timer A mode control: 2 - Continous up 3 constant MC_3 \ Timer A mode control: 3 - Up/Down : TA1CTL_ID<< ( x -- ) 6 lshift ; \ Timer A clock input divider 1 0 constant ID_0 \ Timer A input divider: 0 - /1 1 constant ID_1 \ Timer A input divider: 1 - /2 2 constant ID_2 \ Timer A input divider: 2 - /4 3 constant ID_3 \ Timer A input divider: 3 - /8 : TA1CTL_TASSEL<< ( x -- ) 8 lshift ; \ Timer A clock source select 1 0 constant TASSEL_0 \ Timer A clock source select: 0 - TACLK 1 constant TASSEL_1 \ Timer A clock source select: 1 - ACLK 2 constant TASSEL_2 \ Timer A clock source select: 2 - SMCLK 3 constant TASSEL_3 \ Timer A clock source select: 3 - INCLK \ TA1CCTL0 : Timer1_A3 Capture/Compare Control 0 : TA1CCTL0_CCIFG ( -- x ) %1 0 lshift ; \ Capture/compare interrupt flag : TA1CCTL0_COV ( -- x ) %1 1 lshift ; \ Capture/compare overflow flag : TA1CCTL0_OUT ( -- x ) %1 2 lshift ; \ PWM Output signal if output mode 0 : TA1CCTL0_CCI ( -- x ) %1 3 lshift ; \ Capture input signal (read) : TA1CCTL0_CCIE ( -- x ) %1 4 lshift ; \ Capture/compare interrupt enable : TA1CCTL0_OUTMOD<< ( x -- ) 5 lshift ; \ Output mode 2 0 constant OUTMOD_0 \ PWM output mode: 0 - output only 1 constant OUTMOD_1 \ PWM output mode: 1 - set 2 constant OUTMOD_2 \ PWM output mode: 2 - PWM toggle/reset 3 constant OUTMOD_3 \ PWM output mode: 3 - PWM set/reset 4 constant OUTMOD_4 \ PWM output mode: 4 - toggle 5 constant OUTMOD_5 \ PWM output mode: 5 - Reset 6 constant OUTMOD_6 \ PWM output mode: 6 - PWM toggle/set 7 constant OUTMOD_7 \ PWM output mode: 7 - PWM reset/set : TA1CCTL0_CAP ( -- x ) %1 8 lshift ; \ Capture mode: 1 /Compare mode : 0 : TA1CCTL0_SCCI ( -- x ) %1 10 lshift ; \ Latched capture signal (read) : TA1CCTL0_SCS ( -- x ) %1 11 lshift ; \ Capture sychronize : TA1CCTL0_CCIS<< ( x -- ) 12 lshift ; \ Capture input select 1 0 constant CCIS_0 \ Capture input select: 0 - CCIxA 1 constant CCIS_1 \ Capture input select: 1 - CCIxB 2 constant CCIS_2 \ Capture input select: 2 - GND 3 constant CCIS_3 \ Capture input select: 3 - Vcc : TA1CCTL0_CM<< ( x -- ) 14 lshift ; \ Capture mode 1 0 constant CM_0 \ Capture mode: 0 - disabled 1 constant CM_1 \ Capture mode: 1 - pos. edge 2 constant CM_2 \ Capture mode: 1 - neg. edge 3 constant CM_3 \ Capture mode: 1 - both edges \ TA1CCTL1 : Timer1_A3 Capture/Compare Control 1 : TA1CCTL1_CCIFG ( -- x ) %1 0 lshift ; \ Capture/compare interrupt flag : TA1CCTL1_COV ( -- x ) %1 1 lshift ; \ Capture/compare overflow flag : TA1CCTL1_OUT ( -- x ) %1 2 lshift ; \ PWM Output signal if output mode 0 : TA1CCTL1_CCI ( -- x ) %1 3 lshift ; \ Capture input signal (read) : TA1CCTL1_CCIE ( -- x ) %1 4 lshift ; \ Capture/compare interrupt enable : TA1CCTL1_OUTMOD<< ( x -- ) 5 lshift ; \ Output mode 2 0 constant OUTMOD_0 \ PWM output mode: 0 - output only 1 constant OUTMOD_1 \ PWM output mode: 1 - set 2 constant OUTMOD_2 \ PWM output mode: 2 - PWM toggle/reset 3 constant OUTMOD_3 \ PWM output mode: 3 - PWM set/reset 4 constant OUTMOD_4 \ PWM output mode: 4 - toggle 5 constant OUTMOD_5 \ PWM output mode: 5 - Reset 6 constant OUTMOD_6 \ PWM output mode: 6 - PWM toggle/set 7 constant OUTMOD_7 \ PWM output mode: 7 - PWM reset/set : TA1CCTL1_CAP ( -- x ) %1 8 lshift ; \ Capture mode: 1 /Compare mode : 0 : TA1CCTL1_SCCI ( -- x ) %1 10 lshift ; \ Latched capture signal (read) : TA1CCTL1_SCS ( -- x ) %1 11 lshift ; \ Capture sychronize : TA1CCTL1_CCIS<< ( x -- ) 12 lshift ; \ Capture input select 1 0 constant CCIS_0 \ Capture input select: 0 - CCIxA 1 constant CCIS_1 \ Capture input select: 1 - CCIxB 2 constant CCIS_2 \ Capture input select: 2 - GND 3 constant CCIS_3 \ Capture input select: 3 - Vcc : TA1CCTL1_CM<< ( x -- ) 14 lshift ; \ Capture mode 1 0 constant CM_0 \ Capture mode: 0 - disabled 1 constant CM_1 \ Capture mode: 1 - pos. edge 2 constant CM_2 \ Capture mode: 1 - neg. edge 3 constant CM_3 \ Capture mode: 1 - both edges \ TA1CCTL2 : Timer1_A3 Capture/Compare Control 2 : TA1CCTL2_CCIFG ( -- x ) %1 0 lshift ; \ Capture/compare interrupt flag : TA1CCTL2_COV ( -- x ) %1 1 lshift ; \ Capture/compare overflow flag : TA1CCTL2_OUT ( -- x ) %1 2 lshift ; \ PWM Output signal if output mode 0 : TA1CCTL2_CCI ( -- x ) %1 3 lshift ; \ Capture input signal (read) : TA1CCTL2_CCIE ( -- x ) %1 4 lshift ; \ Capture/compare interrupt enable : TA1CCTL2_OUTMOD<< ( x -- ) 5 lshift ; \ Output mode 2 0 constant OUTMOD_0 \ PWM output mode: 0 - output only 1 constant OUTMOD_1 \ PWM output mode: 1 - set 2 constant OUTMOD_2 \ PWM output mode: 2 - PWM toggle/reset 3 constant OUTMOD_3 \ PWM output mode: 3 - PWM set/reset 4 constant OUTMOD_4 \ PWM output mode: 4 - toggle 5 constant OUTMOD_5 \ PWM output mode: 5 - Reset 6 constant OUTMOD_6 \ PWM output mode: 6 - PWM toggle/set 7 constant OUTMOD_7 \ PWM output mode: 7 - PWM reset/set : TA1CCTL2_CAP ( -- x ) %1 8 lshift ; \ Capture mode: 1 /Compare mode : 0 : TA1CCTL2_SCCI ( -- x ) %1 10 lshift ; \ Latched capture signal (read) : TA1CCTL2_SCS ( -- x ) %1 11 lshift ; \ Capture sychronize : TA1CCTL2_CCIS<< ( x -- ) 12 lshift ; \ Capture input select 1 0 constant CCIS_0 \ Capture input select: 0 - CCIxA 1 constant CCIS_1 \ Capture input select: 1 - CCIxB 2 constant CCIS_2 \ Capture input select: 2 - GND 3 constant CCIS_3 \ Capture input select: 3 - Vcc : TA1CCTL2_CM<< ( x -- ) 14 lshift ; \ Capture mode 1 0 constant CM_0 \ Capture mode: 0 - disabled 1 constant CM_1 \ Capture mode: 1 - pos. edge 2 constant CM_2 \ Capture mode: 1 - neg. edge 3 constant CM_3 \ Capture mode: 1 - both edges \ TA1R : Timer1_A3 Counter Register \ TA1CCR0 : Timer1_A3 Capture/Compare 0 \ TA1CCR1 : Timer1_A3 Capture/Compare 1 \ TA1CCR2 : Timer1_A3 Capture/Compare 2 =================================== Timer0_A3 =================================== \ TA0IV : Timer0_A3 Interrupt Vector Word \ TA0CTL : Timer0_A3 Control : TA0CTL_TAIFG ( -- x ) %1 0 lshift ; \ Timer A counter interrupt flag : TA0CTL_TAIE ( -- x ) %1 1 lshift ; \ Timer A counter interrupt enable : TA0CTL_TACLR ( -- x ) %1 2 lshift ; \ Timer A counter clear : TA0CTL_MC<< ( x -- ) 4 lshift ; \ Timer A mode control 1 0 constant MC_0 \ Timer A mode control: 0 - Stop 1 constant MC_1 \ Timer A mode control: 1 - Up to CCR0 2 constant MC_2 \ Timer A mode control: 2 - Continous up 3 constant MC_3 \ Timer A mode control: 3 - Up/Down : TA0CTL_ID<< ( x -- ) 6 lshift ; \ Timer A clock input divider 1 0 constant ID_0 \ Timer A input divider: 0 - /1 1 constant ID_1 \ Timer A input divider: 1 - /2 2 constant ID_2 \ Timer A input divider: 2 - /4 3 constant ID_3 \ Timer A input divider: 3 - /8 : TA0CTL_TASSEL<< ( x -- ) 8 lshift ; \ Timer A clock source select 1 0 constant TASSEL_0 \ Timer A clock source select: 0 - TACLK 1 constant TASSEL_1 \ Timer A clock source select: 1 - ACLK 2 constant TASSEL_2 \ Timer A clock source select: 2 - SMCLK 3 constant TASSEL_3 \ Timer A clock source select: 3 - INCLK \ TA0CCTL0 : Timer0_A3 Capture/Compare Control 0 : TA0CCTL0_CCIFG ( -- x ) %1 0 lshift ; \ Capture/compare interrupt flag : TA0CCTL0_COV ( -- x ) %1 1 lshift ; \ Capture/compare overflow flag : TA0CCTL0_OUT ( -- x ) %1 2 lshift ; \ PWM Output signal if output mode 0 : TA0CCTL0_CCI ( -- x ) %1 3 lshift ; \ Capture input signal (read) : TA0CCTL0_CCIE ( -- x ) %1 4 lshift ; \ Capture/compare interrupt enable : TA0CCTL0_OUTMOD<< ( x -- ) 5 lshift ; \ Output mode 2 0 constant OUTMOD_0 \ PWM output mode: 0 - output only 1 constant OUTMOD_1 \ PWM output mode: 1 - set 2 constant OUTMOD_2 \ PWM output mode: 2 - PWM toggle/reset 3 constant OUTMOD_3 \ PWM output mode: 3 - PWM set/reset 4 constant OUTMOD_4 \ PWM output mode: 4 - toggle 5 constant OUTMOD_5 \ PWM output mode: 5 - Reset 6 constant OUTMOD_6 \ PWM output mode: 6 - PWM toggle/set 7 constant OUTMOD_7 \ PWM output mode: 7 - PWM reset/set : TA0CCTL0_CAP ( -- x ) %1 8 lshift ; \ Capture mode: 1 /Compare mode : 0 : TA0CCTL0_SCCI ( -- x ) %1 10 lshift ; \ Latched capture signal (read) : TA0CCTL0_SCS ( -- x ) %1 11 lshift ; \ Capture sychronize : TA0CCTL0_CCIS<< ( x -- ) 12 lshift ; \ Capture input select 1 0 constant CCIS_0 \ Capture input select: 0 - CCIxA 1 constant CCIS_1 \ Capture input select: 1 - CCIxB 2 constant CCIS_2 \ Capture input select: 2 - GND 3 constant CCIS_3 \ Capture input select: 3 - Vcc : TA0CCTL0_CM<< ( x -- ) 14 lshift ; \ Capture mode 1 0 constant CM_0 \ Capture mode: 0 - disabled 1 constant CM_1 \ Capture mode: 1 - pos. edge 2 constant CM_2 \ Capture mode: 1 - neg. edge 3 constant CM_3 \ Capture mode: 1 - both edges \ TA0CCTL1 : Timer0_A3 Capture/Compare Control 1 : TA0CCTL1_CCIFG ( -- x ) %1 0 lshift ; \ Capture/compare interrupt flag : TA0CCTL1_COV ( -- x ) %1 1 lshift ; \ Capture/compare overflow flag : TA0CCTL1_OUT ( -- x ) %1 2 lshift ; \ PWM Output signal if output mode 0 : TA0CCTL1_CCI ( -- x ) %1 3 lshift ; \ Capture input signal (read) : TA0CCTL1_CCIE ( -- x ) %1 4 lshift ; \ Capture/compare interrupt enable : TA0CCTL1_OUTMOD<< ( x -- ) 5 lshift ; \ Output mode 2 0 constant OUTMOD_0 \ PWM output mode: 0 - output only 1 constant OUTMOD_1 \ PWM output mode: 1 - set 2 constant OUTMOD_2 \ PWM output mode: 2 - PWM toggle/reset 3 constant OUTMOD_3 \ PWM output mode: 3 - PWM set/reset 4 constant OUTMOD_4 \ PWM output mode: 4 - toggle 5 constant OUTMOD_5 \ PWM output mode: 5 - Reset 6 constant OUTMOD_6 \ PWM output mode: 6 - PWM toggle/set 7 constant OUTMOD_7 \ PWM output mode: 7 - PWM reset/set : TA0CCTL1_CAP ( -- x ) %1 8 lshift ; \ Capture mode: 1 /Compare mode : 0 : TA0CCTL1_SCCI ( -- x ) %1 10 lshift ; \ Latched capture signal (read) : TA0CCTL1_SCS ( -- x ) %1 11 lshift ; \ Capture sychronize : TA0CCTL1_CCIS<< ( x -- ) 12 lshift ; \ Capture input select 1 0 constant CCIS_0 \ Capture input select: 0 - CCIxA 1 constant CCIS_1 \ Capture input select: 1 - CCIxB 2 constant CCIS_2 \ Capture input select: 2 - GND 3 constant CCIS_3 \ Capture input select: 3 - Vcc : TA0CCTL1_CM<< ( x -- ) 14 lshift ; \ Capture mode 1 0 constant CM_0 \ Capture mode: 0 - disabled 1 constant CM_1 \ Capture mode: 1 - pos. edge 2 constant CM_2 \ Capture mode: 1 - neg. edge 3 constant CM_3 \ Capture mode: 1 - both edges \ TA0CCTL2 : Timer0_A3 Capture/Compare Control 2 : TA0CCTL2_CCIFG ( -- x ) %1 0 lshift ; \ Capture/compare interrupt flag : TA0CCTL2_COV ( -- x ) %1 1 lshift ; \ Capture/compare overflow flag : TA0CCTL2_OUT ( -- x ) %1 2 lshift ; \ PWM Output signal if output mode 0 : TA0CCTL2_CCI ( -- x ) %1 3 lshift ; \ Capture input signal (read) : TA0CCTL2_CCIE ( -- x ) %1 4 lshift ; \ Capture/compare interrupt enable : TA0CCTL2_OUTMOD<< ( x -- ) 5 lshift ; \ Output mode 2 0 constant OUTMOD_0 \ PWM output mode: 0 - output only 1 constant OUTMOD_1 \ PWM output mode: 1 - set 2 constant OUTMOD_2 \ PWM output mode: 2 - PWM toggle/reset 3 constant OUTMOD_3 \ PWM output mode: 3 - PWM set/reset 4 constant OUTMOD_4 \ PWM output mode: 4 - toggle 5 constant OUTMOD_5 \ PWM output mode: 5 - Reset 6 constant OUTMOD_6 \ PWM output mode: 6 - PWM toggle/set 7 constant OUTMOD_7 \ PWM output mode: 7 - PWM reset/set : TA0CCTL2_CAP ( -- x ) %1 8 lshift ; \ Capture mode: 1 /Compare mode : 0 : TA0CCTL2_SCCI ( -- x ) %1 10 lshift ; \ Latched capture signal (read) : TA0CCTL2_SCS ( -- x ) %1 11 lshift ; \ Capture sychronize : TA0CCTL2_CCIS<< ( x -- ) 12 lshift ; \ Capture input select 1 0 constant CCIS_0 \ Capture input select: 0 - CCIxA 1 constant CCIS_1 \ Capture input select: 1 - CCIxB 2 constant CCIS_2 \ Capture input select: 2 - GND 3 constant CCIS_3 \ Capture input select: 3 - Vcc : TA0CCTL2_CM<< ( x -- ) 14 lshift ; \ Capture mode 1 0 constant CM_0 \ Capture mode: 0 - disabled 1 constant CM_1 \ Capture mode: 1 - pos. edge 2 constant CM_2 \ Capture mode: 1 - neg. edge 3 constant CM_3 \ Capture mode: 1 - both edges \ TA0R : Timer0_A3 Counter Register \ TA0CCR0 : Timer0_A3 Capture/Compare 0 \ TA0CCR1 : Timer0_A3 Capture/Compare 1 \ TA0CCR2 : Timer0_A3 Capture/Compare 2 =================================== USCI_B0_I2C_Mode =================================== \ UCB0CTL0 : USCI B0 Control Register 0 : UCB0CTL0_UCSYNC ( -- x ) %1 0 lshift ; \ Sync-Mode 0:UART-Mode / 1:SPI-Mode : UCB0CTL0_UCMODE<< ( x -- ) 1 lshift ; \ Sync. Mode: USCI Mode 1 0 constant UCMODE_0 \ Sync. Mode: USCI Mode: 0 1 constant UCMODE_1 \ Sync. Mode: USCI Mode: 1 2 constant UCMODE_2 \ Sync. Mode: USCI Mode: 2 3 constant UCMODE_3 \ Sync. Mode: USCI Mode: 3 : UCB0CTL0_UCMST ( -- x ) %1 3 lshift ; \ Sync. Mode: Master Select : UCB0CTL0_UCMM ( -- x ) %1 5 lshift ; \ Multi-Master Environment : UCB0CTL0_UCSLA10 ( -- x ) %1 6 lshift ; \ 10-bit Slave Address Mode : UCB0CTL0_UCA10 ( -- x ) %1 7 lshift ; \ 10-bit Address Mode \ UCB0CTL1 : USCI B0 Control Register 1 : UCB0CTL1_UCSWRST ( -- x ) %1 0 lshift ; \ USCI Software Reset : UCB0CTL1_UCTXSTT ( -- x ) %1 1 lshift ; \ Transmit START : UCB0CTL1_UCTXSTP ( -- x ) %1 2 lshift ; \ Transmit STOP : UCB0CTL1_UCTXNACK ( -- x ) %1 3 lshift ; \ Transmit NACK : UCB0CTL1_UCTR ( -- x ) %1 4 lshift ; \ Transmit/Receive Select/Flag : UCB0CTL1_UCSSEL<< ( x -- ) 6 lshift ; \ USCI 1 Clock Source Select 1 0 constant UCSSEL_0 \ USCI 0 Clock Source: 0 1 constant UCSSEL_1 \ USCI 0 Clock Source: 1 2 constant UCSSEL_2 \ USCI 0 Clock Source: 2 3 constant UCSSEL_3 \ USCI 0 Clock Source: 3 \ UCB0BR0 : USCI B0 Baud Rate 0 \ UCB0BR1 : USCI B0 Baud Rate 1 \ UCB0I2CIE : USCI B0 I2C Interrupt Enable Register : UCB0I2CIE_UCALIE ( -- x ) %1 0 lshift ; \ Arbitration Lost interrupt enable : UCB0I2CIE_UCSTTIE ( -- x ) %1 1 lshift ; \ START Condition interrupt enable : UCB0I2CIE_UCSTPIE ( -- x ) %1 2 lshift ; \ STOP Condition interrupt enable : UCB0I2CIE_UCNACKIE ( -- x ) %1 3 lshift ; \ NACK Condition interrupt enable \ UCB0STAT : USCI B0 Status Register : UCB0STAT_UCALIFG ( -- x ) %1 0 lshift ; \ Arbitration Lost interrupt Flag : UCB0STAT_UCSTTIFG ( -- x ) %1 1 lshift ; \ START Condition interrupt Flag : UCB0STAT_UCSTPIFG ( -- x ) %1 2 lshift ; \ STOP Condition interrupt Flag : UCB0STAT_UCNACKIFG ( -- x ) %1 3 lshift ; \ NAK Condition interrupt Flag : UCB0STAT_UCBBUSY ( -- x ) %1 4 lshift ; \ Bus Busy Flag : UCB0STAT_UCGC ( -- x ) %1 5 lshift ; \ General Call address received Flag : UCB0STAT_UCSCLLOW ( -- x ) %1 6 lshift ; \ SCL low : UCB0STAT_UCLISTEN ( -- x ) %1 7 lshift ; \ USCI Listen mode \ UCB0RXBUF : USCI B0 Receive Buffer \ UCB0TXBUF : USCI B0 Transmit Buffer \ UCB0I2COA : USCI B0 I2C Own Address : UCB0I2COA_UCOA0 ( -- x ) %1 0 lshift ; \ I2C Own Address 0 : UCB0I2COA_UCOA1 ( -- x ) %1 1 lshift ; \ I2C Own Address 1 : UCB0I2COA_UCOA2 ( -- x ) %1 2 lshift ; \ I2C Own Address 2 : UCB0I2COA_UCOA3 ( -- x ) %1 3 lshift ; \ I2C Own Address 3 : UCB0I2COA_UCOA4 ( -- x ) %1 4 lshift ; \ I2C Own Address 4 : UCB0I2COA_UCOA5 ( -- x ) %1 5 lshift ; \ I2C Own Address 5 : UCB0I2COA_UCOA6 ( -- x ) %1 6 lshift ; \ I2C Own Address 6 : UCB0I2COA_UCOA7 ( -- x ) %1 7 lshift ; \ I2C Own Address 7 : UCB0I2COA_UCOA8 ( -- x ) %1 8 lshift ; \ I2C Own Address 8 : UCB0I2COA_UCOA9 ( -- x ) %1 9 lshift ; \ I2C Own Address 9 : UCB0I2COA_UCGCEN ( -- x ) %1 15 lshift ; \ I2C General Call enable \ UCB0I2CSA : USCI B0 I2C Slave Address : UCB0I2CSA_UCSA0 ( -- x ) %1 0 lshift ; \ I2C Slave Address 0 : UCB0I2CSA_UCSA1 ( -- x ) %1 1 lshift ; \ I2C Slave Address 1 : UCB0I2CSA_UCSA2 ( -- x ) %1 2 lshift ; \ I2C Slave Address 2 : UCB0I2CSA_UCSA3 ( -- x ) %1 3 lshift ; \ I2C Slave Address 3 : UCB0I2CSA_UCSA4 ( -- x ) %1 4 lshift ; \ I2C Slave Address 4 : UCB0I2CSA_UCSA5 ( -- x ) %1 5 lshift ; \ I2C Slave Address 5 : UCB0I2CSA_UCSA6 ( -- x ) %1 6 lshift ; \ I2C Slave Address 6 : UCB0I2CSA_UCSA7 ( -- x ) %1 7 lshift ; \ I2C Slave Address 7 : UCB0I2CSA_UCSA8 ( -- x ) %1 8 lshift ; \ I2C Slave Address 8 : UCB0I2CSA_UCSA9 ( -- x ) %1 9 lshift ; \ I2C Slave Address 9 =================================== TLV_Calibration_Data =================================== \ TLV_ADC10_1_TAG : TLV ADC10_1 TAG \ TLV_ADC10_1_LEN : TLV ADC10_1 LEN \ TLV_DCO_30_TAG : TLV TAG_DCO30 TAG \ TLV_DCO_30_LEN : TLV TAG_DCO30 LEN \ TLV_CHECKSUM : TLV CHECK SUM =================================== ADC10 =================================== \ ADC10DTC0 : ADC10 Data Transfer Control 0 : ADC10DTC0_ADC10FETCH ( -- x ) %1 0 lshift ; \ This bit should normally be reset : ADC10DTC0_ADC10B1 ( -- x ) %1 1 lshift ; \ ADC10 block one : ADC10DTC0_ADC10CT ( -- x ) %1 2 lshift ; \ ADC10 continuous transfer : ADC10DTC0_ADC10TB ( -- x ) %1 3 lshift ; \ ADC10 two-block mode \ ADC10DTC1 : ADC10 Data Transfer Control 1 \ ADC10AE0 : ADC10 Analog Enable 0 \ ADC10CTL0 : ADC10 Control 0 : ADC10CTL0_ADC10SC ( -- x ) %1 0 lshift ; \ ADC10 Start Conversion : ADC10CTL0_ENC ( -- x ) %1 1 lshift ; \ ADC10 Enable Conversion : ADC10CTL0_ADC10IFG ( -- x ) %1 2 lshift ; \ ADC10 Interrupt Flag : ADC10CTL0_ADC10IE ( -- x ) %1 3 lshift ; \ ADC10 Interrupt Enalbe : ADC10CTL0_ADC10ON ( -- x ) %1 4 lshift ; \ ADC10 On/Enable : ADC10CTL0_REFON ( -- x ) %1 5 lshift ; \ ADC10 Reference on : ADC10CTL0_REF2_5V ( -- x ) %1 6 lshift ; \ ADC10 Ref 0:1.5V / 1:2.5V : ADC10CTL0_MSC ( -- x ) %1 7 lshift ; \ ADC10 Multiple SampleConversion : ADC10CTL0_REFBURST ( -- x ) %1 8 lshift ; \ ADC10 Reference Burst Mode : ADC10CTL0_REFOUT ( -- x ) %1 9 lshift ; \ ADC10 Enalbe output of Ref. : ADC10CTL0_ADC10SR ( -- x ) %1 10 lshift ; \ ADC10 Sampling Rate 0:200ksps / 1:50ksps : ADC10CTL0_ADC10SHT<< ( x -- ) 11 lshift ; \ ADC10 Sample Hold Select Bit: 0 0 constant ADC10SHT_0 \ 4 x ADC10CLKs 1 constant ADC10SHT_1 \ 8 x ADC10CLKs 2 constant ADC10SHT_2 \ 16 x ADC10CLKs 3 constant ADC10SHT_3 \ 64 x ADC10CLKs : ADC10CTL0_SREF<< ( x -- ) 13 lshift ; \ ADC10 Reference Select Bit: 0 0 constant SREF_0 \ VR+ = AVCC and VR- = AVSS 1 constant SREF_1 \ VR+ = VREF+ and VR- = AVSS 2 constant SREF_2 \ VR+ = VEREF+ and VR- = AVSS 3 constant SREF_3 \ VR+ = VEREF+ and VR- = AVSS 4 constant SREF_4 \ VR+ = AVCC and VR- = VREF-/VEREF- 5 constant SREF_5 \ VR+ = VREF+ and VR- = VREF-/VEREF- 6 constant SREF_6 \ VR+ = VEREF+ and VR- = VREF-/VEREF- 7 constant SREF_7 \ VR+ = VEREF+ and VR- = VREF-/VEREF- \ ADC10CTL1 : ADC10 Control 1 : ADC10CTL1_ADC10BUSY ( -- x ) %1 0 lshift ; \ ADC10 BUSY : ADC10CTL1_CONSEQ<< ( x -- ) 1 lshift ; \ ADC10 Conversion Sequence Select 0 0 constant CONSEQ_0 \ Single channel single conversion 1 constant CONSEQ_1 \ Sequence of channels 2 constant CONSEQ_2 \ Repeat single channel 3 constant CONSEQ_3 \ Repeat sequence of channels : ADC10CTL1_ADC10SSEL<< ( x -- ) 3 lshift ; \ ADC10 Clock Source Select Bit: 0 0 constant ADC10SSEL_0 \ ADC10OSC 1 constant ADC10SSEL_1 \ ACLK 2 constant ADC10SSEL_2 \ MCLK 3 constant ADC10SSEL_3 \ SMCLK : ADC10CTL1_ADC10DIV<< ( x -- ) 5 lshift ; \ ADC10 Clock Divider Select Bit: 0 0 constant ADC10DIV_0 \ ADC10 Clock Divider Select 0 1 constant ADC10DIV_1 \ ADC10 Clock Divider Select 1 2 constant ADC10DIV_2 \ ADC10 Clock Divider Select 2 3 constant ADC10DIV_3 \ ADC10 Clock Divider Select 3 4 constant ADC10DIV_4 \ ADC10 Clock Divider Select 4 5 constant ADC10DIV_5 \ ADC10 Clock Divider Select 5 6 constant ADC10DIV_6 \ ADC10 Clock Divider Select 6 7 constant ADC10DIV_7 \ ADC10 Clock Divider Select 7 : ADC10CTL1_ISSH ( -- x ) %1 8 lshift ; \ ADC10 Invert Sample Hold Signal : ADC10CTL1_ADC10DF ( -- x ) %1 9 lshift ; \ ADC10 Data Format 0:binary 1:2's complement : ADC10CTL1_SHS<< ( x -- ) 10 lshift ; \ ADC10 Sample/Hold Source Bit: 0 0 constant SHS_0 \ ADC10SC 1 constant SHS_1 \ TA3 OUT1 2 constant SHS_2 \ TA3 OUT0 3 constant SHS_3 \ TA3 OUT2 : ADC10CTL1_INCH<< ( x -- ) 12 lshift ; \ ADC10 Input Channel Select Bit: 0 0 constant INCH_0 \ Selects Channel 0 1 constant INCH_1 \ Selects Channel 1 2 constant INCH_2 \ Selects Channel 2 3 constant INCH_3 \ Selects Channel 3 4 constant INCH_4 \ Selects Channel 4 5 constant INCH_5 \ Selects Channel 5 6 constant INCH_6 \ Selects Channel 6 7 constant INCH_7 \ Selects Channel 7 8 constant INCH_8 \ Selects Channel 8 9 constant INCH_9 \ Selects Channel 9 10 constant INCH_10 \ Selects Channel 10 11 constant INCH_11 \ Selects Channel 11 12 constant INCH_12 \ Selects Channel 12 13 constant INCH_13 \ Selects Channel 13 14 constant INCH_14 \ Selects Channel 14 15 constant INCH_15 \ Selects Channel 15 \ ADC10MEM : ADC10 Memory \ ADC10SA : ADC10 Data Transfer Start Address =================================== USCI_B0_SPI_Mode =================================== \ UCB0CTL0 : USCI B0 Control Register 0 : UCB0CTL0_UCSYNC ( -- x ) %1 0 lshift ; \ Sync-Mode 0:UART-Mode / 1:SPI-Mode : UCB0CTL0_UCMODE<< ( x -- ) 1 lshift ; \ Sync. Mode: USCI Mode 1 0 constant UCMODE_0 \ Sync. Mode: USCI Mode: 0 1 constant UCMODE_1 \ Sync. Mode: USCI Mode: 1 2 constant UCMODE_2 \ Sync. Mode: USCI Mode: 2 3 constant UCMODE_3 \ Sync. Mode: USCI Mode: 3 : UCB0CTL0_UCMST ( -- x ) %1 3 lshift ; \ Sync. Mode: Master Select : UCB0CTL0_UC7BIT ( -- x ) %1 4 lshift ; \ Sync. Mode: Data Bits 0:8-bits / 1:7-bits : UCB0CTL0_UCMSB ( -- x ) %1 5 lshift ; \ Sync. Mode: MSB first 0:LSB / 1:MSB : UCB0CTL0_UCCKPL ( -- x ) %1 6 lshift ; \ Sync. Mode: Clock Polarity : UCB0CTL0_UCCKPH ( -- x ) %1 7 lshift ; \ Sync. Mode: Clock Phase \ UCB0CTL1 : USCI B0 Control Register 1 : UCB0CTL1_UCSWRST ( -- x ) %1 0 lshift ; \ USCI Software Reset : UCB0CTL1_UCSSEL<< ( x -- ) 6 lshift ; \ USCI 1 Clock Source Select 1 0 constant UCSSEL_0 \ USCI 0 Clock Source: 0 1 constant UCSSEL_1 \ USCI 0 Clock Source: 1 2 constant UCSSEL_2 \ USCI 0 Clock Source: 2 3 constant UCSSEL_3 \ USCI 0 Clock Source: 3 \ UCB0BR0 : USCI B0 Baud Rate 0 \ UCB0BR1 : USCI B0 Baud Rate 1 \ UCB0STAT : USCI B0 Status Register : UCB0STAT_UCBUSY ( -- x ) %1 0 lshift ; \ USCI Busy Flag : UCB0STAT_UCOE ( -- x ) %1 5 lshift ; \ USCI Overrun Error Flag : UCB0STAT_UCFE ( -- x ) %1 6 lshift ; \ USCI Frame Error Flag : UCB0STAT_UCLISTEN ( -- x ) %1 7 lshift ; \ USCI Listen mode \ UCB0RXBUF : USCI B0 Receive Buffer \ UCB0TXBUF : USCI B0 Transmit Buffer =================================== USCI_A0_SPI_Mode =================================== \ UCA0CTL0 : USCI A0 Control Register 0 : UCA0CTL0_UCSYNC ( -- x ) %1 0 lshift ; \ Sync-Mode 0:UART-Mode / 1:SPI-Mode : UCA0CTL0_UCMODE<< ( x -- ) 1 lshift ; \ Sync. Mode: USCI Mode 1 0 constant UCMODE_0 \ Sync. Mode: USCI Mode: 0 1 constant UCMODE_1 \ Sync. Mode: USCI Mode: 1 2 constant UCMODE_2 \ Sync. Mode: USCI Mode: 2 3 constant UCMODE_3 \ Sync. Mode: USCI Mode: 3 : UCA0CTL0_UCMST ( -- x ) %1 3 lshift ; \ Sync. Mode: Master Select : UCA0CTL0_UC7BIT ( -- x ) %1 4 lshift ; \ Sync. Mode: Data Bits 0:8-bits / 1:7-bits : UCA0CTL0_UCMSB ( -- x ) %1 5 lshift ; \ Sync. Mode: MSB first 0:LSB / 1:MSB : UCA0CTL0_UCCKPL ( -- x ) %1 6 lshift ; \ Sync. Mode: Clock Polarity : UCA0CTL0_UCCKPH ( -- x ) %1 7 lshift ; \ Sync. Mode: Clock Phase \ UCA0CTL1 : USCI A0 Control Register 1 : UCA0CTL1_UCSWRST ( -- x ) %1 0 lshift ; \ USCI Software Reset : UCA0CTL1_UCSSEL<< ( x -- ) 6 lshift ; \ USCI 1 Clock Source Select 1 0 constant UCSSEL_0 \ USCI 0 Clock Source: 0 1 constant UCSSEL_1 \ USCI 0 Clock Source: 1 2 constant UCSSEL_2 \ USCI 0 Clock Source: 2 3 constant UCSSEL_3 \ USCI 0 Clock Source: 3 \ UCA0BR0 : USCI A0 Baud Rate 0 \ UCA0BR1 : USCI A0 Baud Rate 1 \ UCA0MCTL : USCI A0 Modulation Control \ UCA0STAT : USCI A0 Status Register : UCA0STAT_UCBUSY ( -- x ) %1 0 lshift ; \ USCI Busy Flag : UCA0STAT_UCOE ( -- x ) %1 5 lshift ; \ USCI Overrun Error Flag : UCA0STAT_UCFE ( -- x ) %1 6 lshift ; \ USCI Frame Error Flag : UCA0STAT_UCLISTEN ( -- x ) %1 7 lshift ; \ USCI Listen mode \ UCA0RXBUF : USCI A0 Receive Buffer \ UCA0TXBUF : USCI A0 Transmit Buffer =================================== Special_Function =================================== \ IE1 : Interrupt Enable 1 : IE1_WDTIE ( -- x ) %1 0 lshift ; \ Watchdog Interrupt Enable : IE1_OFIE ( -- x ) %1 1 lshift ; \ Osc. Fault Interrupt Enable : IE1_NMIIE ( -- x ) %1 4 lshift ; \ NMI Interrupt Enable : IE1_ACCVIE ( -- x ) %1 5 lshift ; \ Flash Access Violation Interrupt Enable \ IE2 : Interrupt Enable 2 : IE2_UCA0RXIE ( -- x ) %1 0 lshift ; \ UCA0RXIE : IE2_UCA0TXIE ( -- x ) %1 1 lshift ; \ UCA0TXIE : IE2_UCB0RXIE ( -- x ) %1 2 lshift ; \ UCB0RXIE : IE2_UCB0TXIE ( -- x ) %1 3 lshift ; \ UCB0TXIE \ IFG1 : Interrupt Flag 1 : IFG1_WDTIFG ( -- x ) %1 0 lshift ; \ Watchdog Interrupt Flag : IFG1_OFIFG ( -- x ) %1 1 lshift ; \ Osc. Fault Interrupt Flag : IFG1_PORIFG ( -- x ) %1 2 lshift ; \ Power On Interrupt Flag : IFG1_RSTIFG ( -- x ) %1 3 lshift ; \ Reset Interrupt Flag : IFG1_NMIIFG ( -- x ) %1 4 lshift ; \ NMI Interrupt Flag \ IFG2 : Interrupt Flag 2 : IFG2_UCA0RXIFG ( -- x ) %1 0 lshift ; \ UCA0RXIFG : IFG2_UCA0TXIFG ( -- x ) %1 1 lshift ; \ UCA0TXIFG : IFG2_UCB0RXIFG ( -- x ) %1 2 lshift ; \ UCB0RXIFG : IFG2_UCB0TXIFG ( -- x ) %1 3 lshift ; \ UCB0TXIFG =================================== Port_3_4 =================================== \ P3REN : Port 3 Resistor Enable : P3REN_P0 ( -- x ) %1 0 lshift ; \ P0 : P3REN_P1 ( -- x ) %1 1 lshift ; \ P1 : P3REN_P2 ( -- x ) %1 2 lshift ; \ P2 : P3REN_P3 ( -- x ) %1 3 lshift ; \ P3 : P3REN_P4 ( -- x ) %1 4 lshift ; \ P4 : P3REN_P5 ( -- x ) %1 5 lshift ; \ P5 : P3REN_P6 ( -- x ) %1 6 lshift ; \ P6 : P3REN_P7 ( -- x ) %1 7 lshift ; \ P7 \ P3IN : Port 3 Input : P3IN_P0 ( -- x ) %1 0 lshift ; \ P0 : P3IN_P1 ( -- x ) %1 1 lshift ; \ P1 : P3IN_P2 ( -- x ) %1 2 lshift ; \ P2 : P3IN_P3 ( -- x ) %1 3 lshift ; \ P3 : P3IN_P4 ( -- x ) %1 4 lshift ; \ P4 : P3IN_P5 ( -- x ) %1 5 lshift ; \ P5 : P3IN_P6 ( -- x ) %1 6 lshift ; \ P6 : P3IN_P7 ( -- x ) %1 7 lshift ; \ P7 \ P3OUT : Port 3 Output : P3OUT_P0 ( -- x ) %1 0 lshift ; \ P0 : P3OUT_P1 ( -- x ) %1 1 lshift ; \ P1 : P3OUT_P2 ( -- x ) %1 2 lshift ; \ P2 : P3OUT_P3 ( -- x ) %1 3 lshift ; \ P3 : P3OUT_P4 ( -- x ) %1 4 lshift ; \ P4 : P3OUT_P5 ( -- x ) %1 5 lshift ; \ P5 : P3OUT_P6 ( -- x ) %1 6 lshift ; \ P6 : P3OUT_P7 ( -- x ) %1 7 lshift ; \ P7 \ P3DIR : Port 3 Direction : P3DIR_P0 ( -- x ) %1 0 lshift ; \ P0 : P3DIR_P1 ( -- x ) %1 1 lshift ; \ P1 : P3DIR_P2 ( -- x ) %1 2 lshift ; \ P2 : P3DIR_P3 ( -- x ) %1 3 lshift ; \ P3 : P3DIR_P4 ( -- x ) %1 4 lshift ; \ P4 : P3DIR_P5 ( -- x ) %1 5 lshift ; \ P5 : P3DIR_P6 ( -- x ) %1 6 lshift ; \ P6 : P3DIR_P7 ( -- x ) %1 7 lshift ; \ P7 \ P3SEL : Port 3 Selection : P3SEL_P0 ( -- x ) %1 0 lshift ; \ P0 : P3SEL_P1 ( -- x ) %1 1 lshift ; \ P1 : P3SEL_P2 ( -- x ) %1 2 lshift ; \ P2 : P3SEL_P3 ( -- x ) %1 3 lshift ; \ P3 : P3SEL_P4 ( -- x ) %1 4 lshift ; \ P4 : P3SEL_P5 ( -- x ) %1 5 lshift ; \ P5 : P3SEL_P6 ( -- x ) %1 6 lshift ; \ P6 : P3SEL_P7 ( -- x ) %1 7 lshift ; \ P7 \ P3SEL2 : Port 3 Selection 2 : P3SEL2_P0 ( -- x ) %1 0 lshift ; \ P0 : P3SEL2_P1 ( -- x ) %1 1 lshift ; \ P1 : P3SEL2_P2 ( -- x ) %1 2 lshift ; \ P2 : P3SEL2_P3 ( -- x ) %1 3 lshift ; \ P3 : P3SEL2_P4 ( -- x ) %1 4 lshift ; \ P4 : P3SEL2_P5 ( -- x ) %1 5 lshift ; \ P5 : P3SEL2_P6 ( -- x ) %1 6 lshift ; \ P6 : P3SEL2_P7 ( -- x ) %1 7 lshift ; \ P7 =================================== Calibration_Data =================================== \ CALDCO_16MHZ : DCOCTL Calibration Data for 16MHz \ CALBC1_16MHZ : BCSCTL1 Calibration Data for 16MHz \ CALDCO_12MHZ : DCOCTL Calibration Data for 12MHz \ CALBC1_12MHZ : BCSCTL1 Calibration Data for 12MHz \ CALDCO_8MHZ : DCOCTL Calibration Data for 8MHz \ CALBC1_8MHZ : BCSCTL1 Calibration Data for 8MHz \ CALDCO_1MHZ : DCOCTL Calibration Data for 1MHz \ CALBC1_1MHZ : BCSCTL1 Calibration Data for 1MHz =================================== Port_1_2 =================================== \ P1IN : Port 1 Input : P1IN_P0 ( -- x ) %1 0 lshift ; \ P0 : P1IN_P1 ( -- x ) %1 1 lshift ; \ P1 : P1IN_P2 ( -- x ) %1 2 lshift ; \ P2 : P1IN_P3 ( -- x ) %1 3 lshift ; \ P3 : P1IN_P4 ( -- x ) %1 4 lshift ; \ P4 : P1IN_P5 ( -- x ) %1 5 lshift ; \ P5 : P1IN_P6 ( -- x ) %1 6 lshift ; \ P6 : P1IN_P7 ( -- x ) %1 7 lshift ; \ P7 \ P1OUT : Port 1 Output : P1OUT_P0 ( -- x ) %1 0 lshift ; \ P0 : P1OUT_P1 ( -- x ) %1 1 lshift ; \ P1 : P1OUT_P2 ( -- x ) %1 2 lshift ; \ P2 : P1OUT_P3 ( -- x ) %1 3 lshift ; \ P3 : P1OUT_P4 ( -- x ) %1 4 lshift ; \ P4 : P1OUT_P5 ( -- x ) %1 5 lshift ; \ P5 : P1OUT_P6 ( -- x ) %1 6 lshift ; \ P6 : P1OUT_P7 ( -- x ) %1 7 lshift ; \ P7 \ P1DIR : Port 1 Direction : P1DIR_P0 ( -- x ) %1 0 lshift ; \ P0 : P1DIR_P1 ( -- x ) %1 1 lshift ; \ P1 : P1DIR_P2 ( -- x ) %1 2 lshift ; \ P2 : P1DIR_P3 ( -- x ) %1 3 lshift ; \ P3 : P1DIR_P4 ( -- x ) %1 4 lshift ; \ P4 : P1DIR_P5 ( -- x ) %1 5 lshift ; \ P5 : P1DIR_P6 ( -- x ) %1 6 lshift ; \ P6 : P1DIR_P7 ( -- x ) %1 7 lshift ; \ P7 \ P1IFG : Port 1 Interrupt Flag : P1IFG_P0 ( -- x ) %1 0 lshift ; \ P0 : P1IFG_P1 ( -- x ) %1 1 lshift ; \ P1 : P1IFG_P2 ( -- x ) %1 2 lshift ; \ P2 : P1IFG_P3 ( -- x ) %1 3 lshift ; \ P3 : P1IFG_P4 ( -- x ) %1 4 lshift ; \ P4 : P1IFG_P5 ( -- x ) %1 5 lshift ; \ P5 : P1IFG_P6 ( -- x ) %1 6 lshift ; \ P6 : P1IFG_P7 ( -- x ) %1 7 lshift ; \ P7 \ P1IES : Port 1 Interrupt Edge Select : P1IES_P0 ( -- x ) %1 0 lshift ; \ P0 : P1IES_P1 ( -- x ) %1 1 lshift ; \ P1 : P1IES_P2 ( -- x ) %1 2 lshift ; \ P2 : P1IES_P3 ( -- x ) %1 3 lshift ; \ P3 : P1IES_P4 ( -- x ) %1 4 lshift ; \ P4 : P1IES_P5 ( -- x ) %1 5 lshift ; \ P5 : P1IES_P6 ( -- x ) %1 6 lshift ; \ P6 : P1IES_P7 ( -- x ) %1 7 lshift ; \ P7 \ P1IE : Port 1 Interrupt Enable : P1IE_P0 ( -- x ) %1 0 lshift ; \ P0 : P1IE_P1 ( -- x ) %1 1 lshift ; \ P1 : P1IE_P2 ( -- x ) %1 2 lshift ; \ P2 : P1IE_P3 ( -- x ) %1 3 lshift ; \ P3 : P1IE_P4 ( -- x ) %1 4 lshift ; \ P4 : P1IE_P5 ( -- x ) %1 5 lshift ; \ P5 : P1IE_P6 ( -- x ) %1 6 lshift ; \ P6 : P1IE_P7 ( -- x ) %1 7 lshift ; \ P7 \ P1SEL : Port 1 Selection : P1SEL_P0 ( -- x ) %1 0 lshift ; \ P0 : P1SEL_P1 ( -- x ) %1 1 lshift ; \ P1 : P1SEL_P2 ( -- x ) %1 2 lshift ; \ P2 : P1SEL_P3 ( -- x ) %1 3 lshift ; \ P3 : P1SEL_P4 ( -- x ) %1 4 lshift ; \ P4 : P1SEL_P5 ( -- x ) %1 5 lshift ; \ P5 : P1SEL_P6 ( -- x ) %1 6 lshift ; \ P6 : P1SEL_P7 ( -- x ) %1 7 lshift ; \ P7 \ P1REN : Port 1 Resistor Enable : P1REN_P0 ( -- x ) %1 0 lshift ; \ P0 : P1REN_P1 ( -- x ) %1 1 lshift ; \ P1 : P1REN_P2 ( -- x ) %1 2 lshift ; \ P2 : P1REN_P3 ( -- x ) %1 3 lshift ; \ P3 : P1REN_P4 ( -- x ) %1 4 lshift ; \ P4 : P1REN_P5 ( -- x ) %1 5 lshift ; \ P5 : P1REN_P6 ( -- x ) %1 6 lshift ; \ P6 : P1REN_P7 ( -- x ) %1 7 lshift ; \ P7 \ P2IN : Port 2 Input : P2IN_P0 ( -- x ) %1 0 lshift ; \ P0 : P2IN_P1 ( -- x ) %1 1 lshift ; \ P1 : P2IN_P2 ( -- x ) %1 2 lshift ; \ P2 : P2IN_P3 ( -- x ) %1 3 lshift ; \ P3 : P2IN_P4 ( -- x ) %1 4 lshift ; \ P4 : P2IN_P5 ( -- x ) %1 5 lshift ; \ P5 : P2IN_P6 ( -- x ) %1 6 lshift ; \ P6 : P2IN_P7 ( -- x ) %1 7 lshift ; \ P7 \ P2OUT : Port 2 Output : P2OUT_P0 ( -- x ) %1 0 lshift ; \ P0 : P2OUT_P1 ( -- x ) %1 1 lshift ; \ P1 : P2OUT_P2 ( -- x ) %1 2 lshift ; \ P2 : P2OUT_P3 ( -- x ) %1 3 lshift ; \ P3 : P2OUT_P4 ( -- x ) %1 4 lshift ; \ P4 : P2OUT_P5 ( -- x ) %1 5 lshift ; \ P5 : P2OUT_P6 ( -- x ) %1 6 lshift ; \ P6 : P2OUT_P7 ( -- x ) %1 7 lshift ; \ P7 \ P2DIR : Port 2 Direction : P2DIR_P0 ( -- x ) %1 0 lshift ; \ P0 : P2DIR_P1 ( -- x ) %1 1 lshift ; \ P1 : P2DIR_P2 ( -- x ) %1 2 lshift ; \ P2 : P2DIR_P3 ( -- x ) %1 3 lshift ; \ P3 : P2DIR_P4 ( -- x ) %1 4 lshift ; \ P4 : P2DIR_P5 ( -- x ) %1 5 lshift ; \ P5 : P2DIR_P6 ( -- x ) %1 6 lshift ; \ P6 : P2DIR_P7 ( -- x ) %1 7 lshift ; \ P7 \ P2IFG : Port 2 Interrupt Flag : P2IFG_P0 ( -- x ) %1 0 lshift ; \ P0 : P2IFG_P1 ( -- x ) %1 1 lshift ; \ P1 : P2IFG_P2 ( -- x ) %1 2 lshift ; \ P2 : P2IFG_P3 ( -- x ) %1 3 lshift ; \ P3 : P2IFG_P4 ( -- x ) %1 4 lshift ; \ P4 : P2IFG_P5 ( -- x ) %1 5 lshift ; \ P5 : P2IFG_P6 ( -- x ) %1 6 lshift ; \ P6 : P2IFG_P7 ( -- x ) %1 7 lshift ; \ P7 \ P2IES : Port 2 Interrupt Edge Select : P2IES_P0 ( -- x ) %1 0 lshift ; \ P0 : P2IES_P1 ( -- x ) %1 1 lshift ; \ P1 : P2IES_P2 ( -- x ) %1 2 lshift ; \ P2 : P2IES_P3 ( -- x ) %1 3 lshift ; \ P3 : P2IES_P4 ( -- x ) %1 4 lshift ; \ P4 : P2IES_P5 ( -- x ) %1 5 lshift ; \ P5 : P2IES_P6 ( -- x ) %1 6 lshift ; \ P6 : P2IES_P7 ( -- x ) %1 7 lshift ; \ P7 \ P2IE : Port 2 Interrupt Enable : P2IE_P0 ( -- x ) %1 0 lshift ; \ P0 : P2IE_P1 ( -- x ) %1 1 lshift ; \ P1 : P2IE_P2 ( -- x ) %1 2 lshift ; \ P2 : P2IE_P3 ( -- x ) %1 3 lshift ; \ P3 : P2IE_P4 ( -- x ) %1 4 lshift ; \ P4 : P2IE_P5 ( -- x ) %1 5 lshift ; \ P5 : P2IE_P6 ( -- x ) %1 6 lshift ; \ P6 : P2IE_P7 ( -- x ) %1 7 lshift ; \ P7 \ P2SEL : Port 2 Selection : P2SEL_P0 ( -- x ) %1 0 lshift ; \ P0 : P2SEL_P1 ( -- x ) %1 1 lshift ; \ P1 : P2SEL_P2 ( -- x ) %1 2 lshift ; \ P2 : P2SEL_P3 ( -- x ) %1 3 lshift ; \ P3 : P2SEL_P4 ( -- x ) %1 4 lshift ; \ P4 : P2SEL_P5 ( -- x ) %1 5 lshift ; \ P5 : P2SEL_P6 ( -- x ) %1 6 lshift ; \ P6 : P2SEL_P7 ( -- x ) %1 7 lshift ; \ P7 \ P2REN : Port 2 Resistor Enable : P2REN_P0 ( -- x ) %1 0 lshift ; \ P0 : P2REN_P1 ( -- x ) %1 1 lshift ; \ P1 : P2REN_P2 ( -- x ) %1 2 lshift ; \ P2 : P2REN_P3 ( -- x ) %1 3 lshift ; \ P3 : P2REN_P4 ( -- x ) %1 4 lshift ; \ P4 : P2REN_P5 ( -- x ) %1 5 lshift ; \ P5 : P2REN_P6 ( -- x ) %1 6 lshift ; \ P6 : P2REN_P7 ( -- x ) %1 7 lshift ; \ P7 \ P1SEL2 : Port 1 Selection 2 : P1SEL2_P0 ( -- x ) %1 0 lshift ; \ P0 : P1SEL2_P1 ( -- x ) %1 1 lshift ; \ P1 : P1SEL2_P2 ( -- x ) %1 2 lshift ; \ P2 : P1SEL2_P3 ( -- x ) %1 3 lshift ; \ P3 : P1SEL2_P4 ( -- x ) %1 4 lshift ; \ P4 : P1SEL2_P5 ( -- x ) %1 5 lshift ; \ P5 : P1SEL2_P6 ( -- x ) %1 6 lshift ; \ P6 : P1SEL2_P7 ( -- x ) %1 7 lshift ; \ P7 \ P2SEL2 : Port 2 Selection 2 : P2SEL2_P0 ( -- x ) %1 0 lshift ; \ P0 : P2SEL2_P1 ( -- x ) %1 1 lshift ; \ P1 : P2SEL2_P2 ( -- x ) %1 2 lshift ; \ P2 : P2SEL2_P3 ( -- x ) %1 3 lshift ; \ P3 : P2SEL2_P4 ( -- x ) %1 4 lshift ; \ P4 : P2SEL2_P5 ( -- x ) %1 5 lshift ; \ P5 : P2SEL2_P6 ( -- x ) %1 6 lshift ; \ P6 : P2SEL2_P7 ( -- x ) %1 7 lshift ; \ P7 =================================== System_Clock =================================== \ BCSCTL3 : Basic Clock System Control 3 : BCSCTL3_LFXT1OF ( -- x ) %1 0 lshift ; \ Low/high Frequency Oscillator Fault Flag : BCSCTL3_XT2OF ( -- x ) %1 1 lshift ; \ High frequency oscillator 2 fault flag : BCSCTL3_XCAP<< ( x -- ) 2 lshift ; \ XIN/XOUT Cap 0 0 constant XCAP_0 \ XIN/XOUT Cap : 0 pF 1 constant XCAP_1 \ XIN/XOUT Cap : 6 pF 2 constant XCAP_2 \ XIN/XOUT Cap : 10 pF 3 constant XCAP_3 \ XIN/XOUT Cap : 12.5 pF : BCSCTL3_LFXT1S<< ( x -- ) 4 lshift ; \ Mode 0 for LFXT1 (XTS = 0) 0 constant LFXT1S_0 \ Mode 0 for LFXT1 : Normal operation 1 constant LFXT1S_1 \ Mode 1 for LFXT1 : Reserved 2 constant LFXT1S_2 \ Mode 2 for LFXT1 : VLO 3 constant LFXT1S_3 \ Mode 3 for LFXT1 : Digital input signal : BCSCTL3_XT2S<< ( x -- ) 6 lshift ; \ Mode 0 for XT2 0 constant XT2S_0 \ Mode 0 for XT2 : 0.4 - 1 MHz 1 constant XT2S_1 \ Mode 1 for XT2 : 1 - 4 MHz 2 constant XT2S_2 \ Mode 2 for XT2 : 2 - 16 MHz 3 constant XT2S_3 \ Mode 3 for XT2 : Digital input signal \ DCOCTL : DCO Clock Frequency Control : DCOCTL_MOD0 ( -- x ) %1 0 lshift ; \ Modulation Bit 0 : DCOCTL_MOD1 ( -- x ) %1 1 lshift ; \ Modulation Bit 1 : DCOCTL_MOD2 ( -- x ) %1 2 lshift ; \ Modulation Bit 2 : DCOCTL_MOD3 ( -- x ) %1 3 lshift ; \ Modulation Bit 3 : DCOCTL_MOD4 ( -- x ) %1 4 lshift ; \ Modulation Bit 4 : DCOCTL_DCO0 ( -- x ) %1 5 lshift ; \ DCO Select Bit 0 : DCOCTL_DCO1 ( -- x ) %1 6 lshift ; \ DCO Select Bit 1 : DCOCTL_DCO2 ( -- x ) %1 7 lshift ; \ DCO Select Bit 2 \ BCSCTL1 : Basic Clock System Control 1 : BCSCTL1_RSEL0 ( -- x ) %1 0 lshift ; \ Range Select Bit 0 : BCSCTL1_RSEL1 ( -- x ) %1 1 lshift ; \ Range Select Bit 1 : BCSCTL1_RSEL2 ( -- x ) %1 2 lshift ; \ Range Select Bit 2 : BCSCTL1_RSEL3 ( -- x ) %1 3 lshift ; \ Range Select Bit 3 : BCSCTL1_DIVA<< ( x -- ) 4 lshift ; \ ACLK Divider 0 0 constant DIVA_0 \ ACLK Divider 0: /1 1 constant DIVA_1 \ ACLK Divider 1: /2 2 constant DIVA_2 \ ACLK Divider 2: /4 3 constant DIVA_3 \ ACLK Divider 3: /8 : BCSCTL1_XTS ( -- x ) %1 6 lshift ; \ LFXTCLK 0:Low Freq. / 1: High Freq. : BCSCTL1_XT2OFF ( -- x ) %1 7 lshift ; \ Enable XT2CLK \ BCSCTL2 : Basic Clock System Control 2 : BCSCTL2_DIVS<< ( x -- ) 1 lshift ; \ SMCLK Divider 0 0 constant DIVS_0 \ SMCLK Divider 0: /1 1 constant DIVS_1 \ SMCLK Divider 1: /2 2 constant DIVS_2 \ SMCLK Divider 2: /4 3 constant DIVS_3 \ SMCLK Divider 3: /8 : BCSCTL2_SELS ( -- x ) %1 3 lshift ; \ SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK : BCSCTL2_DIVM<< ( x -- ) 4 lshift ; \ MCLK Divider 0 0 constant DIVM_0 \ MCLK Divider 0: /1 1 constant DIVM_1 \ MCLK Divider 1: /2 2 constant DIVM_2 \ MCLK Divider 2: /4 3 constant DIVM_3 \ MCLK Divider 3: /8 : BCSCTL2_SELM<< ( x -- ) 6 lshift ; \ MCLK Source Select 0 0 constant SELM_0 \ MCLK Source Select 0: DCOCLK 1 constant SELM_1 \ MCLK Source Select 1: DCOCLK 2 constant SELM_2 \ MCLK Source Select 2: XT2CLK/LFXTCLK 3 constant SELM_3 \ MCLK Source Select 3: LFXTCLK =================================== _INTERRUPTS =================================== \ TRAPINT $FFE0 TRAPINT \ PORT1 $FFE4 Port 1 \ PORT2 $FFE6 Port 2 \ ADC10 $FFEA ADC10 \ USCIAB0TX $FFEC USCI A0/B0 Transmit \ USCIAB0RX $FFEE USCI A0/B0 Receive \ TIMER0_A1 $FFF0 Timer0)A CC1, TA0 \ TIMER0_A0 $FFF2 Timer0_A CC0 \ WDT $FFF4 Watchdog Timer \ COMPARATORA $FFF6 Comparator A \ TIMER1_A1 $FFF8 Timer1_A CC1-4, TA1 \ TIMER1_A0 $FFFA Timer1_A CC0 \ NMI $FFFC Non-maskable